1. Field of the Invention
The present invention relates to thin-film, interconnected multilayer boards for packaging very-large-scale integrated circuits (VLSI circuits), terminal resistors, capacitors, etc. at a high density and also to processes for their fabrication. Further, this invention is concerned with modules making use of such interconnected multilayer boards and also with computers having such modules.
2. Description of the Related Art
A conventional process for the fabrication of an interconnected multilayer board will first be described, taking by way of example the flow chart shown in FIGS. 9(a) through 9(g).
As is illustrated in FIG. 9(a), a metallic underconductor layer 92 which can also serve as an electrode for plating is formed over the entire area of an upper surface of a substrate 91. On the upper surface of the metallic under-conductor layer 92, a resist 93 windowed in the form of a desired conductor line pattern is formed as depicted in FIG. 9(b). Plating is then conducted using, as electrodes, the metallic underconductor layer 92 exposed in channels 94 so that, as shown in FIG. 9(c), the channels 94 in the resist 93 are selectively filled with a conductor to form conductors, via-hole conductors, glands or through-hole conductors 95. After the resist 93 is next removed to expose the conductors 95 as depicted in FIG. 9(d), the metallic under-conductor layer 92 is removed at portions other than the portions facing and contacting the conductors 95 as shown in FIG. 9(e). Next, as is illustrated in FIG. 9(f), an insulating layer 96 is formed with a polymer over the entire upper surface of the substrate 91 such that the conductors 95 are covered by the insulating layer 96. As is depicted in FIG. 9(g), by grinding or the like, the upper surfaces of the conductors 95 are exposed and the surface of the insulating layer 96 is formed into a flat surface. The above steps are repeated successively a plurality of times, whereby an interconnected multilayer board is fabricated.
Relevant technology is disclosed, for example, in Proceedings of the 34th ECC (Electronic Component Conference), 82-87 (1984).
The most serious problem of the above-described conventional technique resides in the need for the steps of forming and removing a resist, the steps of forming and removing a metallic under-conductor layer, the step of forming an insulating layer and the step of making the insulating layer flat for each of layers such as conductor layer, gland layer and via-hole conductor layer. The conventional technique therefore includes many steps, resulting in long lead time and poor mass productivity.
The conventional technique is accompanied not only by the need for such many steps but also by many other problems such as the inclusion of technically troublesome steps, for example, the need for grinding and polishing of an insulating polymer layer and the difficulties in the elimination of dust particles such as grinding and polishing powder by washing.